Forum Discussion
Altera_Forum
Honored Contributor
9 years agoHello PietervanderStar,
thanks for your hint! I've now solved the problem this way:-- wait state
process
begin
wait until clk_50MHZ'event and clk_50MHZ = '1';
if count_1KHZ /= 24999 then
count_1KHZ <= count_1KHZ + 1;
else
count_1KHZ <= 0;
clk_1KHZ <= not clk_1KHZ;
end if;
end process;
process (clk_1KHZ)
begin
if (clk_choice = '0') then
if rising_edge(clk_1KHZ) then
if (count_individual_timer < timer_time) then
count_individual_timer <= count_individual_timer + 1;
individual_timer_EN <= '0';
else
individual_timer_EN <= '1';
count_individual_timer <= 0;
end if;
end if;
else
individual_timer_EN <= '1';
end if;
end process;