hi all, I have a question regarding the organisation of modules. At the moment I program my Verilog and VHDL designs in a bunch of files and make a .vqm file at the to have a snapshot of all files together. This works fine unless you want to pass parameters/generics up to the SOPC builder through a vqm-file. Is there another good way to merge a whole design into one handy file AND use parameters with the Quartus tool-suite? Thank you for any hint or suggestion. Stefan

You might not get a good response on this one because users generally don't do this. They write everything in separate HDL files because it is easier to organize and edit that way. For organization, they might keep it all in a /src sub directory and point to it from Quartus, but I have almost never seen them all in one file. (Unless it's a library of components or it's a real small number of files, like 3). Also, how come you are calling it a .vqm rather than just a .v? A .vqm is a verilog file used as a netlist to pass synthesis results from 3rd party synthesizers into Quartus. For example, Synplify writes out a .vqm which is a structural representation of its synthesis results. Quartus can write out similar .vqms. I believe the synthesizer is optimized to read in .vqms under the assumption that this is what they are, structural models. So if you put generic verilog into a file and call it a .vqm, you might get sub-optimal results. I don't know this for sure, but would suggest keeping it a .v or .verilog file.

You can dump a VQM from Quartus, rename it to .V, and then edit to add parameters if you like. You may need a little search and replace action to convert from the escaped string names to something more civilized. I do that occasionally to preserve low level synthesis results. There isn't a mechanism to get a VQM with the original parameters intact, unfortunately.

The reason I do this is to have an easy manageable module that is used like a library without 20 and more files (like a precompiled library in C) but I see that this was not the idea of the vqm files. Another point is that there are bdfs in the designs that can't be included into a SOPC module. Using the vqm seemed to solve that problem... (of course I could also convert them into verlilog/vhdl, but this is a huge work because the conversion by Quartus don't produce really usable code - hmmm just tried it again, 7.2sp1 may come over with that problem ) So it may be easier to use the source files as they are even the file list of a SOPC project will be long... The point to integrate the parameters into a vqm file is not usable because I have e.g. array size parameters that are odd to replace in a vqm file. Thank you for your answers.

Here, There is no restriction to put a complete design in one file, either Verilog or VHDL, including multiple module respectively entity defintions and packages. For *.bdf files, Quartus has the option to generate HDL. The code may also need some edition to improve readability, but it's probably better than using *.vqm output. Regards, Frank

The time is here and Quartus II doesn't support the vqm writer for cyclone III devices. What would be the equivalent to a .vqm file from older families for the cyclone III device? thanks

vqm and parameters | Altera Community

12 Replies

Altera_Forum
Honored Contributor
18 years ago
You might not get a good response on this one because users generally don't do this. They write everything in separate HDL files because it is easier to organize and edit that way. For organization, they might keep it all in a /src sub directory and point to it from Quartus, but I have almost never seen them all in one file. (Unless it's a library of components or it's a real small number of files, like 3).

Also, how come you are calling it a .vqm rather than just a .v? A .vqm is a verilog file used as a netlist to pass synthesis results from 3rd party synthesizers into Quartus. For example, Synplify writes out a .vqm which is a structural representation of its synthesis results. Quartus can write out similar .vqms. I believe the synthesizer is optimized to read in .vqms under the assumption that this is what they are, structural models. So if you put generic verilog into a file and call it a .vqm, you might get sub-optimal results. I don't know this for sure, but would suggest keeping it a .v or .verilog file.
Altera_Forum
Honored Contributor
18 years ago
You can dump a VQM from Quartus, rename it to .V, and then edit to add parameters if you like. You may need a little search and replace action to convert from the escaped string names to something more civilized. I do that occasionally to preserve low level synthesis results.

There isn't a mechanism to get a VQM with the original parameters intact, unfortunately.
Altera_Forum
Honored Contributor
18 years ago
The reason I do this is to have an easy manageable module that is used like a library without 20 and more files (like a precompiled library in C) but I see that this was not the idea of the vqm files.
Another point is that there are bdfs in the designs that can't be included into a SOPC module. Using the vqm seemed to solve that problem... (of course I could also convert them into verlilog/vhdl, but this is a huge work because the conversion by Quartus don't produce really usable code - hmmm just tried it again, 7.2sp1 may come over with that problem )

So it may be easier to use the source files as they are even the file list of a SOPC project will be long...

The point to integrate the parameters into a vqm file is not usable because I have e.g. array size parameters that are odd to replace in a vqm file.

Thank you for your answers.
Altera_Forum
Honored Contributor
18 years ago
Here,

There is no restriction to put a complete design in one file, either Verilog or VHDL, including multiple module respectively entity defintions and packages. For *.bdf files, Quartus has the option to generate HDL. The code may also need some edition to improve readability, but it's probably better than using *.vqm output.

Regards,
Frank
Altera_Forum
Honored Contributor
17 years ago
The time is here and Quartus II doesn't support the vqm writer for cyclone III devices.
What would be the equivalent to a .vqm file from older families for the cyclone III device?

thanks
Altera_Forum
Honored Contributor
17 years ago
Grumble grumble toil and trouble.

You can target Cyclone II, make a VQM, just reuse the VQM on C3 99% of the time. The exceptions would be related to exotic IO standards. (Quartus synthesis will translate the WYS cells as appro).

Let me know if that doesn't work for you. There may be other methods.
Altera_Forum
Honored Contributor
17 years ago
what do you consider exotic IO?

Doesn't quartus II generate an edif file after synthesis?
Altera_Forum
Honored Contributor
17 years ago
Dedicated SERDES units, Hard IP protocol blocks, that kind of thing.

Which come to think of it aren't on Cyclone 3 devices. Should work fine.
Altera_Forum
Honored Contributor
17 years ago
that's a good work around got a simple piece of code working by using one target device to create the .vqm and going back to the one I need. Excellent, thanks for that suggestion
Altera_Forum
Honored Contributor
17 years ago
It may have EDIF capability. I would definitely suggest the VQM though. The most common 3rd party synthesis entry to Quartus uses VQM's.

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vqm and parameters

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