Altera_Forum
Honored Contributor
18 years agovqm and parameters
hi all,
I have a question regarding the organisation of modules. At the moment I program my Verilog and VHDL designs in a bunch of files and make a .vqm file at the to have a snapshot of all files together. This works fine unless you want to pass parameters/generics up to the SOPC builder through a vqm-file. Is there another good way to merge a whole design into one handy file AND use parameters with the Quartus tool-suite? Thank you for any hint or suggestion. Stefan