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Altera_Forum
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11 years ago

Virtual JTAG counter to TDO

Hi everyone, I'm new in FPGA verilog system. I have a DE0 nano from Terasic (http://www.terasic.com.tw/cgi-bin/page/archive.pl?language=english&no=593&from=fb-like). During my little train...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Sorry to come back to you....

Someone have an idea ? I search again and again.

If I ceate an FIFO instance, Is it possible that resolve my problem ? And how can I implement that in my design ?

Thanks for helping