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Altera_Forum's avatar
Altera_Forum
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17 years ago

Viewing variable values in VHDL

Hi, I am quite new to VHDL and Quartus II. I have coded a 16x8 RAM using VHDL in Quartus but I don't know how to check it because I cannot view the array variable where the data is stored in wa...
Altera_Forum's avatar
Altera_Forum
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17 years ago

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P.S.: As you already find out, the Quartus integrated simulator isn't able to display RAM cell internal data. This can be done very comfortable with ModelSIm. The Megafunction user guide shows also ModelSim simulation examples.

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I found http://www.altera.com/literature/ug/ug_ram.pdf. I am not sure if thats what u were refering to. However, its in Verilog. Do U know of any one in VHDL..?

Thanks..

By the way, in that example, they have "rden" and "wren" instead of just "RW" and they have a seperate output port "q". Is there any difference is using bidirectional port..?