Viewing PLL clock internal signals

I'm still not sure where you're having problems and are trying to figure out. The PLL should do a very good job of aligning the clock as you request. There will be a small variance due to global clock tree routing, but that will be on the orger of picoseconds. What is it that you're trying to see? Note that a functional simulation, doesn't know anything about the actual device, so there will be no timing info except what you put into it. Static Timing Analysis is the method for finding delays.