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Altera_Forum
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18 years ago

Viewing PLL clock internal signals

Hi everyone, My current design is clocked by a 250MHz master clock. Within the FPGA, I use a divide by 16 PLL with two clock outputs c0, c1 with different phase in order 1) to clock RAM blo...
Altera_Forum's avatar
Altera_Forum
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18 years ago

Rysc,

Indeed, I've been able to view my PLL output clocks in a functional sim. In the end, it simply showed me the signals were ...as required in the PLL settings !

I usually have a great confidence in Qts but for this time, I had a doubt because of a "strange" sample behavioral waveforms (see enclosed) generated for my PLL design and likely due to a too much short displayed waveform time period.

Many Thanks to both of you for sharing your experience in this forum !

Your answers give precious clues and encouragement that help me for a deeper reading of the pretty complex "PLL & Clock networks" chapter of the Stratix II device handbook (that I would have sub-titled "36 ways to loose your clocks in a labyrinth" ;-) )

Oliver