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Altera_Forum
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18 years ago

Viewing PLL clock internal signals

Hi everyone, My current design is clocked by a 250MHz master clock. Within the FPGA, I use a divide by 16 PLL with two clock outputs c0, c1 with different phase in order 1) to clock RAM blo...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

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I would recommend using TimeQuest, in which case you need to put a clock constraint on the input clock and a derive_pll_clocks command.

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Or "derive_pll_clocks -create_base_clocks", which will make TimeQuest use the PLL megafunction settings to automatically produce the create_clock on the base clock feeding the PLL as well as the generated clocks driven by the PLL.