Viewing PLL clock internal signals

Technically, you should be able to find the outputs of the PLL in a functional sim, and I believe they should be delayed correctly, but it will be an ideal delay, i.e. exactly what you entered into the PLL settings.

But you really don't want to use the simulator to analyze paths between domains. You have to check each register to register path between the domains(unless you trust a few represent them all). You have to check them on every compile(or trust things never change). What you really want to do is static timing analysis between the domains, to guarantee data transfers properly between them.

That being said, by entering the clock constraints in the PLL, timin analysis already knows how they're related, so there's probably not much, if any, to do. (I would recommend using TimeQuest, in which case you need to put a clock constraint on the input clock and a derive_pll_clocks command). In TimeQuest you can report timing on specific paths, i.e. you can list all paths from c0 to c1.