Viewing Data in Bus Lines without I/O Pins in Waveform Editor [Newbie].

--- Quote Start ---

You can use SignalTap to view signals inside your FPGA.

Search on Altera's site for 'signaltap' or see the following tutorial: signaltap tutorial (ftp://ftp.altera.com/up/pub/altera_material/10.1/tutorials/verilog/signaltap.pdf)

Regards,

Alex

--- Quote End ---

Can it probe without an actual FPGA board? I only need to see the data in my bus lines in simulation after compiling.