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Altera_Forum's avatar
Altera_Forum
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11 years ago

VHDL writing in memory

Hi,

I have a hardware design running on a Cyclone IV FPGA and a software part running on a Nios II cpu on the very same FPGA. Both are sharing a dual port FPGA memory. I want the hardware part to write data on the memory and the software part to read it. The reading seems to be OK but the writing is not. Here is the VHDL code I use: 

library ieee;use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
entity ctrl is
    port(
        data : out std_logic_vector(7 downto 0);
        wen : out std_logic := '0';
        addr : out std_logic_vector(14 downto 0):=(others=>'0');
        clk : in std_logic);
end ctrl;
architecture rtl of ctrl is
    signal step : integer := 1;
begin
    process(clk)
    begin
        if clk'event and clk='1' then
            data <= "00000001";
            if step<4 then
                step <= step+1;
            end if;
            addr <= std_logic_vector(to_unsigned(step, addr'length));
            wen <= '1';
        end if;
    end process;
end rtl;

What I'd expect is the values written at addresses 2, 3 and 4 to be 1 but I only read 1 at address 4, others are 0.

I'm sure I'm messing something up in the sequential and concurrent statements but I can't solve this.

Could someone help me?

Thanks.

17 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    it looks fine to me, code will generate addresses 1 to 4 and write 1 on sequential clocks. But this is a simple controller. Do you need to hold write enable for any length of time other than 1 clock (because when it reaches 4, it will write the value 0x00000001 to the memory forever? Where is the code for the memory?

    As a side note: you shouldnt be using the std_logic_arith library. Apart from being a non-standard library, it has conflicts with numeric_std. numeric_std is the IEEE standard library.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    I think such code is optimised off to no registers so address is given 4 only

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    I knew that for the libraries, I surely have forgotten this when writing. It's corrected.

    I don't find the memory signals documentation so the hold time may not be correct.

    Do you know where I can find this documentation?
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Here's my new code to have a large hold time: 

    library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ctrl is
    port(
        data        : out std_logic_vector(7 downto 0);
        wen        : out std_logic := '0';
        addr        : out std_logic_vector(14 downto 0):=(others=>'0');
        clk        : in std_logic);
end ctrl;
architecture rtl of ctrl is
    signal step : integer := 1;
    signal hold : integer := 0;
begin
    
    process(clk)
    begin
        if clk'event and clk='1' then
            if step<5 then
                if hold=10 then
                    step <= step+1;
                    hold <= 0;
                end if;
                hold <= hold+1;
                wen <= '1';
            else
                wen <= '0';
            end if;
            data <= "00000001";
            addr <= std_logic_vector(to_unsigned(step, addr'length));
        end if;
    end process;
end rtl;

    Now addresses 1 and 2 are equal to 1 when others are 0. I don't understand what's happening.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    --- Quote Start ---

    Here's my new code to have a large hold time: 

    library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ctrl is
    port(
        data        : out std_logic_vector(7 downto 0);
        wen        : out std_logic := '0';
        addr        : out std_logic_vector(14 downto 0):=(others=>'0');
        clk        : in std_logic);
end ctrl;
architecture rtl of ctrl is
    signal step : integer := 1;
    signal hold : integer := 0;
begin
    
    process(clk)
    begin
        if clk'event and clk='1' then
            if step<5 then
                if hold=10 then
                    step <= step+1;
                    hold <= 0;
                end if;
                hold <= hold+1;
                wen <= '1';
            else
                wen <= '0';
            end if;
            data <= "00000001";
            addr <= std_logic_vector(to_unsigned(step, addr'length));
        end if;
    end process;
end rtl;

    Now addresses 1 and 2 are equal to 1 when others are 0. I don't understand what's happening.

    --- Quote End ---

    insert hold <= hold + 1;

    before the if condition of reset it to zero
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    --- Quote Start ---

    I don't understand your sentence.

    --- Quote End --- 

    
process(clk) 
begin       
if clk'event and clk='1' then            
    if step<5 then
        hold <= hold+1;                
        if hold=10 then                     
             step <= step+1;                     
             hold <= 0;                 
       end if;                 
       wen <= '1';             
   else                 
       wen <= '0';             
   end if;             
   data <= "00000001";             
   addr <= std_logic_vector(to_unsigned(step, addr'length));         
end if;     
end process;
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    That works but I don't understand what is really different. Can you explain?

    Also I have to make the hold time to be at least 8 clock cycles. Is there a document telling that?

    Thank you anyway.