VHDL writing in memory

process(clk) 
begin       
if clk'event and clk='1' then            
    if step<5 then
        hold <= hold+1;                
        if hold=10 then                     
             step <= step+1;                     
             hold <= 0;                 
       end if;                 
       wen <= '1';             
   else                 
       wen <= '0';             
   end if;             
   data <= "00000001";             
   addr <= std_logic_vector(to_unsigned(step, addr'length));         
end if;     
end process;