VHDL writing in memory

Here's my new code to have a large hold time:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ctrl is
    port(
        data        : out std_logic_vector(7 downto 0);
        wen        : out std_logic := '0';
        addr        : out std_logic_vector(14 downto 0):=(others=>'0');
        clk        : in std_logic);
end ctrl;
architecture rtl of ctrl is
    signal step : integer := 1;
    signal hold : integer := 0;
begin
    
    process(clk)
    begin
        if clk'event and clk='1' then
            if step<5 then
                if hold=10 then
                    step <= step+1;
                    hold <= 0;
                end if;
                hold <= hold+1;
                wen <= '1';
            else
                wen <= '0';
            end if;
            data <= "00000001";
            addr <= std_logic_vector(to_unsigned(step, addr'length));
        end if;
    end process;
end rtl;