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Altera_Forum
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11 years ago

VHDL Variables: Is it combinational code inside a clocked process?

Hello all Since the VHDL variables topic strikes as a little bit odd even to VHDL designers who have some experience I would like to ask about VHDL variables in order to clarify a few things. ...
Altera_Forum's avatar
Altera_Forum
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11 years ago

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Is there any way to force an error if a 'variable' ends up being a register?

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Luckily not, I'd say :)

The question, IMHO, indicates you have to study the 'nature of variables' a bit deeper.