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Another question is that maybe inside the clocked process I need to make a variable assignment. Is it possible to split the clocked if in two (so have two if(rising edge)) inside the same process and in between make asynchronous variable assignments?
process(clk)
variable t1 : std_logic;
variable t2 : std_logic;
begin
t1 := A and B;
if rising_edge(clk) then
Yb <= t1;
end if;
Y <= t1 XOR Yb;
t2 := A or B;
if rising_edge(clk) then
Yc <= t2 OR Y;
end if;
end process;
Is this mixture possible?
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according to JosyB any coding style accepted by tools should be ok and I agree.
Your code may work for what you want but then one will ask why not use signal instead of variable t1 since it is outside clock edge and hence combinatorial (always).
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