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Altera_Forum
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11 years ago

VHDL Variables: Is it combinational code inside a clocked process?

Hello all Since the VHDL variables topic strikes as a little bit odd even to VHDL designers who have some experience I would like to ask about VHDL variables in order to clarify a few things. ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

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Can you do this test and provide the RTL diagram again?

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You can try this yourself too, you know?

I doesn't make a difference the register called 't1' is now called 't2' :)