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Altera_Forum
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11 years ago

VHDL Variables: Is it combinational code inside a clocked process?

Hello all Since the VHDL variables topic strikes as a little bit odd even to VHDL designers who have some experience I would like to ask about VHDL variables in order to clarify a few things. ...
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Altera_Forum
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11 years ago

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The assignment ....

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Josyb can you please try doing again test3 but now with using another variable t2 to store t1 before setting Yb? 


process(clk)
   variable t1 : std_logic;
   variable t2 : std_logic;
begin
   if rising_edge(clk) then
      t1 := A and B;
      t2 := t1;
      Yb <= t1;
   end if;
   Y <= t2;                        -- does this attempt fail to export asynchronous t2?
end process;

Can you do this test and provide the RTL diagram again?