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Altera_Forum
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11 years ago

VHDL Variables: Is it combinational code inside a clocked process?

Hello all Since the VHDL variables topic strikes as a little bit odd even to VHDL designers who have some experience I would like to ask about VHDL variables in order to clarify a few things. ...
Altera_Forum's avatar
Altera_Forum
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11 years ago

The Quartus compiler seems to create a combinational and a registered variant of variable t1 and uses it to fed the different expressions containing t1 respectively. Interestingly, the functionally identical register t1 and D~reg0 are kept separate.

I think, it makes no sense to say variable t1 is not registered. Another example of registered variable usage is the Quartus binary counter template. 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
entity test is
    Port ( clk: in std_logic;
           A: in   STD_LOGIC;
           B: in   STD_LOGIC;
           C : out   STD_LOGIC;
           D : out   STD_LOGIC;
           E : out   STD_LOGIC);
end test;
 
architecture rtl of test is
begin
    process (clk)
    variable t1: std_logic;
    begin
        if rising_edge(clk) then
          C <= t1;
          t1 := A and B;
          D <= t1;
        end if;
        E <= t1;
    end process;
end rtl;