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Altera_Forum
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11 years ago

VHDL Variables: Is it combinational code inside a clocked process?

Hello all Since the VHDL variables topic strikes as a little bit odd even to VHDL designers who have some experience I would like to ask about VHDL variables in order to clarify a few things. ...
Altera_Forum's avatar
Altera_Forum
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11 years ago

Well it has to do with the involvement of t2. Did you get any warnings? Because t1 now has no reset value.

If you have put the assignment of t4 inside the clocked if (it would still be combinational) and assign it to Y5 outside the clocked if then would Y5 still be combinational?

By answering to this question i also solve the asynchronous propagation of my variables outside of the process (as soon as the variables do not interact with clocked variables or signals, as we saw here with t1 and t2)