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Altera_Forum
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11 years ago

VHDL Variables: Is it combinational code inside a clocked process?

Hello all Since the VHDL variables topic strikes as a little bit odd even to VHDL designers who have some experience I would like to ask about VHDL variables in order to clarify a few things. ...
Altera_Forum's avatar
Altera_Forum
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11 years ago

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Why does t1 become a register?

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Puzzles me too :)

It would have been very nice had it stayed combinatorial.

This may be one of the oddities Aprado hinted at. Modelsim may behave differently than Quartus II. Until now I've only used variables as I show in my first code example. (Playing safe)