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Altera_Forum
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11 years ago

VHDL Variables: Is it combinational code inside a clocked process?

Hello all Since the VHDL variables topic strikes as a little bit odd even to VHDL designers who have some experience I would like to ask about VHDL variables in order to clarify a few things. ...
Altera_Forum's avatar
Altera_Forum
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11 years ago

You are right but I think it's a matter of readibility and avoiding mistakes.

I find it more easy to read splitting the RTL into a combination process and a sequential process. So, no need for variable. when you need the _next value(comb) right away in the sequential process just use the LVALUE (next) in the decision making.

It's always harder to spot errors in simulation using Variables and simulation/synthesis mismatch ocurrs more.

YMMV