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Altera_Forum
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11 years ago

VHDL Variables: Is it combinational code inside a clocked process?

Hello all Since the VHDL variables topic strikes as a little bit odd even to VHDL designers who have some experience I would like to ask about VHDL variables in order to clarify a few things. ...
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Altera_Forum
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11 years ago

Oh. Another question came up though.

What happens when the designer wants to export asynchronously a variable from a clocked process?

Declaring a signal and assigning it to the variable inside the clocked process would infer a register...

I suppose doing the assignment after the "clocked" IF, ELSEIF(rising edge) would still keep the signal asynchronous...right?