vhdl testbench issue in modelsim

I found a solution. It works when I make the following change to the procedure:

procedure dl_rx_gen (

signal clk : in std_logic;

signal encoded_symbol : in std_logic_vector(13 downto 0);

signal dl_serial_out : out std_logic ) is

begin

wait for 1 ps;

-- loop for each half bit of encoded symbol

for i in encoded_symbol'range loop

dl_serial_out <= encoded_symbol(i);

wait for dl_bit_period/2; -- two values per bit period for manchester encoding

end loop;

end procedure;

It seems that the simulator did not like the fact that the encoded_symbol value was getting set and that value was being used to set dl_serial_out all in the same instant in time.