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Altera_Forum
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16 years ago

vhdl testbench issue in modelsim

I am having a problem in modelsim-altera with a vhdl testbench I have set up to generate a serial data stream. I created a procedure to generate the serial stream as such: -- create procedure...
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Altera_Forum
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16 years ago

OK. Understood. I know that I have seen strange things in simulation before when I have messed up event timing and created a delta delay issue. In your case, you do indicate to wait for a fixed period of time before each new event, so I don't see that this could be a delta delay related issue.