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Altera_Forum
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16 years ago

vhdl testbench issue in modelsim

I am having a problem in modelsim-altera with a vhdl testbench I have set up to generate a serial data stream. I created a procedure to generate the serial stream as such: -- create procedure...
Altera_Forum's avatar
Altera_Forum
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16 years ago

I did intend the signal to be asynchronous to the clock, as that is how it will be in the application. The input goes through a synchronizer and the design performs clock recovery.