vhdl testbench issue in modelsim

I don't know that I can answer your question, but here are a few observations about your code:

(1) It looks like you intend for your events to happen synchronous to the rising and falling edges of your clock, but you do not actually refer to 'clk' inside the procedure.

(2) Is dl_bit_period equal to the period of 'clk'?

How I might tweak the procedure code to align your events to clock edges:

-- code fragment (assumes encoded_symbol'length is an even number)

for i in 1 to encoded_symbol'length/2 loop

wait until rising_edge(clk);

dl_serial_out <= encoded_symbol(i);

wait until falling_edge(clk);

dl_serial_out <= encoded_symbol(i);

end loop;