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Altera_Forum
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13 years ago

VHDL test bench

I don't know how to write test bench coding and i don't know how to see the output.I am writing a simple programme of and gate below: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LO...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

for the stimulus, you write whatever you wan to input a, and watch the result come out on signal b.

eg:

a <= '0';

wait for 100 ms;

a <= '1';

wait for 100 ms;

a <= '0;

You need a simulator like modelsim to run this code.