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Altera_Forum
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11 years ago

VHDL Syntheis Problem with Quartus -II 64 : RISING_EDGE ,ERROR :10822,10028,10029

Hi Friends, I am trying to implement a communication protocol in FPGA with VHDL. I am using Qaurtus-II 64 for logic synthesis. As a part of my implementation I had to implement a state machine for t...
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Altera_Forum
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11 years ago

Synthesis requires that if you want to use clock edge assignment then do it at start of process. You may do that after reset statement but otherwise it is strictly the very start.