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Altera_Forum's avatar
Altera_Forum
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11 years ago

VHDL Slot Machine

I am trying to make a program on a DE-1 board. It is a slot machine. The board will use 3 buttons. One for manual stopping numbers, one for automatically stopping all the numbers, and one to reset. The autostop portion will use a random number generator. I have no idea what is going wrong with this and I know there is a lot. Can somebody help? I attached my entire vhd file. It is also right here:

Library ieee;

use ieee.std_logic_1164.ALL;

use ieee.std_logic_arith.ALL;

use ieee.math_real.ALL;

entity project is

port ( manualStop, autoStop, reset, clock : in std_logic;

ssd3, ssd2, ssd1, ssd0 : out std_logic_vector(0 to 6));

end project;

architecture arch of project is

type display is array(0 to 9) of std_logic_vector(0 to 6);

constant displayMap: display := ("0000001", "1001111", "0010010", "0000110",

"1001100", "0100100", "0100000", "0001111", "0000000", "0000100");

type display2 is array(0 to 3) of std_logic_vector(0 to 6);

constant winDisplay: display2 := ("0000110", "1001111", "0001001", "0001000");

constant loseDisplay: display2 := ("1110001", "0000001", "0100100", "0110000");

signal slowClock : std_logic := '0';

begin

process(clock)

variable counter : integer := 0;

begin

if rising_edge(clock) then

if (counter = 200000) then --24Mhz/60hz/2

slowClock <= not slowClock;

counter := 0;

else

counter := counter + 1;

end if;

end if;

end process;

process(slowClock)

variable spin1 : integer := 1;

variable spin2 : integer := 1;

variable spin3 : integer := 1;

variable spin4 : integer := 1;

variable fini**** : integer := 0;

variable value1 : integer := 0;

variable value2 : integer := 2;

variable value3 : integer := 3;

variable value4 : integer := 6;

variable rand: real;

variable s1 : positive := 1;

variable s2 : positive := 1;

variable waiter: integer := 1;

begin

if (rising_edge(slowClock)) then

loop

if( spin1 = 1 ) then

value1 := ((value1 + 1) mod 9);

end if;

if( spin2 = 1 ) then

value2 := (value2 + 1) mod 9;

end if;

if( spin3 = 1 ) then

value3 := (value3 + 1) mod 9;

end if;

if( spin4 = 1 ) then

value4 := (value4 + 1) mod 9;

end if;

wait for 300 ms;

ssd3 <= displayMap(value4);

ssd2 <= displayMap(value3);

ssd1 <= displayMap(value2);

ssd0 <= displayMap(value1);

if (fini**** = 1) then

UNIFORM(s1, s2, rand);

waiter := INTEGER(TRUNC(rand*10.0));

for I in 1 to waiter loop

if( spin1 = 1 ) then

value1 := (value1 + 1) mod 9;

end if;

if( spin2 = 1) then

value2 := (value2 + 1) mod 9;

end if;

if( spin3 = 1 ) then

value3 := (value3 + 1) mod 9;

end if;

if( spin4 = 1 ) then

value4 := (value4 + 1) mod 9;

end if;

wait for 300 ms;

ssd3 <= displayMap(value4);

ssd2 <= displayMap(value3);

ssd1 <= displayMap(value2);

ssd0 <= displayMap(value1);

end loop;

if ( spin1 = 1 ) then

spin1 := 0;

elsif ( spin2 = 1 ) then

spin2 := 0;

elsif ( spin3 = 1 ) then

spin3 := 0;

elsif ( spin4 = 1 ) then

spin4 := 0;

end if;

elsif ( manualStop = '0' ) then

if ( spin1 = 1 ) then

spin1 := 0;

elsif ( spin2 = 1 ) then

spin2 := 0;

elsif ( spin3 = 1 ) then

spin3 := 0;

elsif ( spin4 = 1 ) then

spin4 := 0;

end if;

elsif ( autoStop = '0' ) then

fini**** := 1;

elsif ( reset = '0' ) then

spin1 := 1;

spin2 := 1;

spin3 := 1;

spin4 := 1;

fini**** := 0;

value1 := 0;

value2 := 2;

value3 := 3;

value4 := 6;

end if;

if ( spin1 = 0 ) and ( spin2 = 0 ) and ( spin3 = 0 ) and ( spin4 = 0 ) then

if ( value1 = 0 ) and ( value2 = 0 ) and ( value3 = 0 ) and ( value4 = 0 ) then

while ( reset = '1' ) loop

wait for 1000 ms;

ssd3 <= winDisplay(value4);

ssd2 <= winDisplay(value3);

ssd1 <= winDisplay(value2);

ssd0 <= winDisplay(value1);

wait for 1000 ms;

ssd3 <= displayMap(value4);

ssd2 <= displayMap(value3);

ssd1 <= displayMap(value2);

ssd0 <= displayMap(value1);

end loop;

else

while ( reset = '1' ) loop

wait for 1000 ms;

ssd3 <= loseDisplay(value4);

ssd2 <= loseDisplay(value3);

ssd1 <= loseDisplay(value2);

ssd0 <= loseDisplay(value1);

wait for 1000 ms;

ssd3 <= displayMap(value4);

ssd2 <= displayMap(value3);

ssd1 <= displayMap(value2);

ssd0 <= displayMap(value1);

end loop;

end if;

end if;

end loop;

end if;

end process;

end arch;

please help

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    What exactly is going wrong?

    I assume you know you cannot synthesise this code, as it is full of all sorts of unsynthesisable bits. I assume it's a simulation only model.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    Interesting , but I agree with Tricky, I think anything's possible but I would be inclined to start with an example that works on the DE-1 board in the HDL you are familiar with.

    I have worked in Verilog and VHDL and for starting off ... Verilog may be easier to map to hardware ... I assume this is a design example as there are arguments for FPGA designs, Programmable controller based designs .. whatever design methodology, the Random Number Generator ( RNG ) is key and when electronics were first introduced to slot machines some governments forced vendors to still have mechanical moving parts ( wheels ) as a source of randomness. That I guess is just history now.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    Alright thanks. Could someone start me out? I just need it to infinite loop at the start and increment the display numbers. I don't need buttons at all. I think I can do that myself. It is just starting out. I need to do it in VHDL. thanks.