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Altera_Forum
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12 years ago

vhdl signed multiplication

how to convert the following unsigned 8x8 multiplication program to "signed 8x8 multiplication"...??? library IEEE; use IEEE.std_logic_1164.all; entity vmul8x8p is port ( X: in STD_LOGIC_VECTOR (7...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

what are you talking about?

my code works for synthesisable VHDL and testbenches.