VHDL question

Hi,

not quite sure, if this adresses your question, but you can either define vectors e.g.

CONSTANT Const : STD_LOGIC_VECTOR (3 DOWNTO 0) := "xxxx"; --place bits here

SIGNAL Changing : STD_LOGIC_VECTOR (11 DOWNTO 0); -- changing Bits

SIGNAL Data_to_DAC : STD_LOGIC_VECTOR (15 DOWNTO 0); -- Data to be sent to DAC

and combine the Data_to_DAC prior sending it to the DAC by

Data_to_DAC <= Constant&Changing;

this results in Bit 15..12 of Data_to_DAC are Bit 3..0 of Const and Bit 11..0 of Data_to_DAC being Bit 11..0 of Changing with the constant bits being defined in the upper section of the VHDL code.

Other way is to define only Data_to_DAC with assignment in code being

Data_to_DAC (15 DOWNTO 12) <= "xxxx"; -- place the constant bits here Data_to_DAC (11 DOWNTO 0) <= Changing; -- or direct the signal which shall be sent

All roads lead to Rome...

Sincerely, Carlhermann