Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

VHDL Loop Statement error...loop must terminate within 10,000 iterations

I have this module of source code:

procedure init_mem_data (signal mem : out mem_ty)is

variable buf : line;

file infile : text ; -- s in "data.txt" ;

variable word : std_logic_vector(7 downto 0);

variable i : integer;

variable good : boolean;

begin

FILE_OPEN(infile,"mycmd_single.txt",READ_MODE);

i := 0;

while not ( endfile(infile) or (i >= mem_depth ) ) loop

readline(infile, buf);

hread(buf,word);

mem(i) <= word ;

i := i + 1;

end loop;

FILE_CLOSE(infile);

end init_mem_data;

but i am having error that,

Error (10536): VHDL Loop Statement error at mem.vhd(38): loop must terminate within 10,000 iterations

what should i do?

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    To initialise a ram for synthesis it needs to be a function that is run at initialisation of tha ram, not a procedure that is run in a process.

    This is exactly the kind of code that would be very useful for synthesis (if it was a function), but in there wisdom Altera have still not managed to support it for VHDL, whereas it works fine in Verilog and Xilinx have no problems with it.

    Please Please Please raise a support request with Altera asking for this enhancement to be added to Quartus.