VHDL Loop Statement error...loop must terminate within 10,000 iterations

To initialise a ram for synthesis it needs to be a function that is run at initialisation of tha ram, not a procedure that is run in a process.

This is exactly the kind of code that would be very useful for synthesis (if it was a function), but in there wisdom Altera have still not managed to support it for VHDL, whereas it works fine in Verilog and Xilinx have no problems with it.

Please Please Please raise a support request with Altera asking for this enhancement to be added to Quartus.