Honored Contributor
Honored ContributorI typed in your VHDL source, compiled it (Quartus 13) planned pins: a LED on pins Q and Qp, J K and C on switches.
When clock = '1' also J and K high, the output q and qp go to the input which changes the output. The result is weak light of LED's because output changes with a frequency determined by the propagation delay. One of two leds is full on and the other LED off when clock is low. Which one of the LED's depends on the moment the clock is going low. Solution: insertion just before the end architecture line a wait on (c); statement, however correct syntax for VHDL it is not accepted by the quartus compiler because the compiler omits sensitivity list (c), and hence announces the stripped wait on as a fatal error Tks Tricky on this forum for his/her help
