Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

VHDL JK FlipFlop Error, Please help

Hello. As you can see in the figure 1, We can make a JK flipflop with 2 ANDs and 2 NORs and two internal signals. So I've written a very simple code in ModelSim to make and simulate a JK FlipF...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Changing the seed just changes how the fitter places the design. The seed is actually based on your source code and the fit seed, so you cannot get reproducible results. Asynchronous logic in FPGAs is prone to all sorts of variation in timing, the first being the placement, but also fluctuations in voltage, temperature and process (ie. one chip is not identical to another chip).

Basically, asynchronous logic in an FPGA is not usually a good idea.

to D4N005H: your code now simulates, but will not be anything like the simulation on hardware. You're at the mercy of the variability I mentioned above.