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Altera_Forum
Honored Contributor
9 years agoIt worked!! The only problem was I should have also update the "work library" of the software each time I recompile the VHDL files. Also I've added the delays when internal signals wanted to get info from Q an Qp and it works like a a JK Latch, I guess (apparently). Here is the results and the modified VHDL file:
https://i.imgsafe.org/2c9d185abe.jpg https://i.imgsafe.org/2c9d100dd9.jpg Thank you for your replies. edit: --- Quote Start --- Greetings All: Has there been any simulation of the JK Flip-Flop been successful? I have been looking at that to see why Quartus makes warnings on latches or any 'Found combinational loop' issues. Now I see why that creates a warning. I had to add a reset, before that it woke up in 'unknown' state in simulation (Quartus 9.1 using .vwf by the way). I tried to make an 'edge clock detector', ie. having an invertion, and say 'edge = '1' when clock = '1' and clock_n = '1' else '0', but that was optimized away by Quartus, and I didn't make it to add the LCELL part to add the propagation delay yet. So I made the clock to a 2% cycle (50% clock always caused oscillation with J & K hi) and tried some seeds, and it made to work properly with 'seed 9'. That's interesting, however, if you have a project with that everywhere, the chances of having all of them not going into oscillation approaches zero, thus why the warning. I recommend using a register using the 'if rising_edge(clock)' and define what the four input sates require for the output pin responses. I have attached the project using the Quartus 9.1 version, with the part EP2C25FC7 for 'DE1 Altera', and it uses the built in simulation. If any others products or compilation programs are used, it may need trying other seed values, many don't work properly. I hope all find that interesting. --- Quote End --- Well as I stated in this message, it apparently works now. About the code, yes it is kinda interesting to see why that happens. Actually my project was for education and we were not allowed to use clocks or flipflops or registers (we ourselves should make them) and I guess your approach is not only better but also suitable for professional basis.