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Ive run and tested the code - I dont know what code you're compiling to get the error you are, but I just got an iteration error because Q depends on Qp which depends on Q. The errors you are reporting are because of the old issue. did you forget to recompile the code and restart the simulation?
To make this model correctly, you need to put delays between q and qp, but these are not synthessiable.
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I always recompile and restart the simulation, I'm sure I've tested the newest compiled VHDL file. And about the delay, since I'm new to this software, would you tell me how to add delays? I coulnd't find a clue to do so.
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