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Honored Contributor

8 years ago

VHDL inout port in gate-level simulation

Hi, I have a design with an bidirectional bus (defined as inout) at the very top level. In module: HWID : inout std_logic_vector(7 downto 0); . . HWID <= data_out ...

Gianfranco9635

New Contributor

1 year ago

I have the same problem, but my port became output and not buffer. Anyone solve this?

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VHDL inout port in gate-level simulation

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