VHDL inout port in gate-level simulation

Hi Tobyn,

I have exactly the same issue. Did you find a solution for Quartus buffer generating?

Because if I change manually in .vho the BUFFER to INOUT, on simulation the bus is Undefined state!

Thanks,

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Hi,

I now understand what is going on. I looked at the .vho Altera compiled my design into and the inout port has been converted from inout to buffer type! It also converted all out ports to buffers as well. That explains why ModelSim complains about multiple drivers: it doesn't like anything in my test bench writing to the buffer port.

ENTITY     RF_module_top IS
    PORT (
    \Rise_Edge_P(n)\ : IN std_logic := '0';
    \Fall_Edge_P(n)\ : IN std_logic := '0';
    HWID : BUFFER std_logic_vector(7 DOWNTO 0);
    nRead : IN std_logic;
.
.
    nWrite : IN std_logic
    );
END RF_module_top;

I still don't get why Altera is doing this... Anyone know how to get around this?

Thanks,

Tobyn

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