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gyuunyuu's avatar
gyuunyuu
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5 years ago
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VHDL IEEE 1076-2019 "Conditional analysis tool directives" in Intel Quartus and ModelSim

The VHDL IEEE 1076-2019 was released late last year. One of its feature are "Conditional analysis tool directives" that make it possible for us to check what tool is analysing the code when it is executed.

I have found that Microsemi Libero's synthesis tool Synopsys Synplify ME version P-2019.03M-SP1-1, January 2020 that comes with Libero 12.4 has the "Conditional analysis tool directives" within it. This can be seen inside the release notes of Synplify ME.

How far is Altera from incorporating this features into their program and also what about ModelSim?

  • RichardT_altera's avatar
    RichardT_altera
    5 years ago

    Hi,

    The VHDL-19 "Conditional analysis tool directives" currently planned to incorporate in Quartus next year. (subject to change).
    Please allow me to close the case for now and you are welcome to reply/tag my name here or open a new case if you would like to get an update on this feature.

    Best Regards,
    Shyan Yew

14 Replies

  • RichardT_altera's avatar
    RichardT_altera
    Icon for Super Contributor rankSuper Contributor
    5 years ago

    Hi,

    Unfortunately, I have no knowledge of this but I will consult with our internal team.
    Please allow us some time to check on this.

    Thanks.

    • gyuunyuu's avatar
      gyuunyuu
      Icon for Contributor rankContributor
      5 years ago

      When inferior programs like Synplify and ActiveHDL can have this feature introduced into them this year, it does not make sense why the posh ones like Quartus and ModelSim do not even plan to introduce them in. This is my conclusion based on what I have discovered so far.

      • RichardT_altera's avatar
        RichardT_altera
        Icon for Super Contributor rankSuper Contributor
        5 years ago

        Unfortunately, the VHDL-19 "Conditional analysis tool directives" is not incorporated in Quartus tool currently.
        The good news is we have a plan to support Vhdl-19, we are working with them to add conditional analysis tool directive" in our tool as well. Though we can not provide you an ETA, rest assured that our engineering team shall definitely work on this.