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Altera_Forum's avatar
Altera_Forum
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8 years ago

[VHDL] how to manage lib name depending on the design entry?

Hi All, I want to use the different library names for the same Le's say I have a VHDL file with the following lines: library mylib_1;use mylib_1.abc.all; But, when I'm go...
Altera_Forum's avatar
Altera_Forum
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8 years ago

In Verilog, there is "`define" where the names/paths might be defined

In VHDL, there are generics. But as far as I understand, they canoot help in this case...

The import package (like in SystemVerilog) is there something similar in VHDL?

In VHDL, can I include different files (like `include in Verilog) depending on configuration?