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Altera_Forum
Honored Contributor
8 years ago[VHDL] how to manage lib name depending on the design entry?
Hi All, I want to use the different library names for the same Le's say I have a VHDL file with the following lines: library mylib_1;use mylib_1.abc.all; But, when I'm go...
Altera_Forum
Honored Contributor
8 years agoyou might be able to have a (tcl) script generate source code, but why do you need to switch?