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Altera_Forum
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15 years ago

VHDL: How to initialize RAM from file?

Good timings! I find in internet-space this vhdl codе: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.STD_LOGIC_...
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Altera_Forum
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15 years ago

RAM initialization from files through textio library functions is only supported by ModelSim and other simulators, but not by Quartus. For synthesis, you can only use *.hex or *.mif files together with a RAM MegaFunction instance. Verilog readfunctions for binary files are supported by Quartus in constrast.