VHDL getting Array elements with std_logic_vector

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I mean you can keep CollisionReg logic as it is then save to ram then use inputs as address to this ram.

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The present logic won't infer RAM as is. The border initialization can be easily achieved as power-up content. Repeating it at runtime can be only done in a sequential process, one address per clock cycle.

As another issue, the design expects to read old data on the same port (addressed by XHead/YHead). That's no possible in a single address cycle with Cyclone II.