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Altera_Forum
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13 years ago

VHDL getting Array elements with std_logic_vector

Hello, I'm having some trouble synthesizing my code, I'm running out of logic cells on my DE2 Altera board. I want to use the values from 4 std_logic_vectors(7 downto 0) to retrieve the e...
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Altera_Forum
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13 years ago

Your array CollisionReg requires 120x160 registers i.e. 19,200. It also requires logic cells for its assignments

Your DidCollide is one bit register but requires 2^16 tests and this is a candidate for moving to ram. I mean you can keep CollisionReg logic as it is then save to ram then use inputs as address to this ram.