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Altera_Forum
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13 years ago

VHDL getting Array elements with std_logic_vector

Hello, I'm having some trouble synthesizing my code, I'm running out of logic cells on my DE2 Altera board. I want to use the values from 4 std_logic_vectors(7 downto 0) to retrieve the e...
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Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

A reasonable way is to implement CollisonReg in internal RAM, changing the code to fulfill the requirements for RAM inference. The most important restriction is that you can't access more than two memory locations at a time if you utilize the dual-port feature. This means that the basic program algorithm has to be redesigned.