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Altera_Forum
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12 years ago

VHDL Generator

Hello i've written a VHDL generator in Python ( https://github.com/andrecp/vhdl_gen ), feel free to use and give feedback! The idea is to generate the entity,architecture and signals from a simple...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Hehe i don't know about MyHDL but my project aims to be really simple, i was going to make it do more things but then i realized that it would just add extra complexity and i wouldn't use it. The way it is today i just use it to generate my new designs and save me the time to type all the ports, library declarations, process declarations and regs <= next.

Cheers