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Altera_Forum
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11 years ago

VHDL Fixed point package with Quartus

Hello! I am trying to use the VHDL Fixed-point package fixed_pkg with Quartus II (11.0 sp1). http://www.vhdl.org/fphld/vhdl.html The package works fine except when trying to define a two dime...
Altera_Forum's avatar
Altera_Forum
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11 years ago

Its possibly falling over because you have GVal as a top level port. Its recommended to use only std_logic_vector, signed or unsigned for top level ports. I bet it doesnt like the -ve indices for the top level ports.

Make fGab an std_logic_vector, and see what happens: 


fGab : out std_logic_vector(5 downto 0);
...
fGab <= to_slv(GMTest(0,0));