VHDL FILE_OPEN does not return correct status in Quartus

Any alternate for this ? I am trying to simulate an instruction sequence that i have written in file. The contents of the file looks as follows:

20020005
2003000c
2067fff7

Is there any way i can read these values and assign them to signals, or changing the tool is the only option ?

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The problem here is that Quartus does not support memory initialisation from a text file in VHDL. I raised an enhancement request for this about 8 years ago, because Xilinx XST always has allowed the use of textio to initialise a ram. Annoyingly, Quartus does support this in verilog.

Just a NOTE: if it did support it - then you are doing it in the wrong way anway - it needs to be done via a function at initialisation time, not runtime in a process.

If the initialisation is easily done via a function, then Quartus does support initialisation via a function (unless it involves textio)

Otherwise your only option is to create a .mif file.

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