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I see.
In some VHDL book it seems that "when" implicitly creates a process that internally uses if instead. This of course is exactly what I wanted to avoid (even though I suppose when all cases are covered the compiler can optimize out the FlipFlops that the process needs to hold the sequential states.
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All assignments outside a process are implicit processes sensitive to every signal on the right hand side of the assignment. "when" is just a way of creating a mux. There are many ways to do exactly the same thing. Look at the following code blocks - they all do exactly the same thing.
output <= A when threebits = "000"
else B when ( threebits = "001" or threebits = "010" )
else C;
out_mux : with threebits select
output <= A when "000", --single case
<= B when "001" | "010", -- 2 states set the same case,
<= C when others; -- catch all the reset of the states
process(threebits, A, B, C)
begin
if threebits = "000" then output <= A;
elsif ( threebits = "001" or threebits = "010" ) then output <= B;
else output <= C;
end if;
end process;
With all of these, you have to explicitly say each case. They are only good when you have a small number of cases, otherwise it is best to use loops like you have already done. If you tried to do the above with your load, you'd have to define 64 explicit cases.
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so instead of
load(i) <= '1' when (conv_integer(address) = i) else '0';
I'd better write something like
load(i) <= not (conv_integer(address) xor i';
Would this avoid the problem from ground up ?
-Michael
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this second method has no meaning, because you cannot xor an integer with anything, or invert it, or assing it directly to a std_logic_vector.
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